The Higher Order Hausdorff Voronoi Diagram and Vlsi Critical Area Extraction for Via-blocks

We extend the Voronoi diagram framework to compute the critical area of a circuit layout [15, 12, 16, 13, 14] with the ability to accurately compute critical area for via-blocks on via and contact layers in the presence of multilayer loops, redundant vias, and redundant interconnects. Critical area is a measure reflecting the sensitivity of a VLSI design to random defects during IC manufacturing. The method is based on concepts of the higher order Hausdorff Voronoi diagram of point clusters in the plane. We investigate structural properties of the order-k Hausdorff Voronoi diagram and present a simple iterative approach that computes the ordinary Hausdorff Voronoi diagram of iteratively determined clusters of points. We highlight simplifications in the L∞ metric, a metric of practical interest in VLSI critical area extraction.